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HUF76129P3, HUF76129S3S
Data Sheet January 2003
56A, 30V, 0.016 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs
These N-Channel power MOSFETs are manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. Formerly developmental type TA76129.
Features
* Logic Level Gate Drive * 56A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.016 * Temperature Compensating PSPICE(R) Model * Temperature Compensating SABER(c) Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER HUF76129P3 HUF76129S3S PACKAGE TO-220AB TO-263AB BRAND 76129P 76129S
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF76129S3ST.
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE
JEDEC TO-263AB
DRAIN (FLANGE)
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (R GS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 20 56 35 34 Figure 4 Figures 6, 17, 18 105 0.83 -40 to 150 300 260 W W/oC
oC oC oC
V V V A A A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC
30 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 11) ID = 56A, VGS = 10V (Figure 9, 10) ID = 35A, VGS = 5V (Figure 9) ID = 34A, VGS = 4.5V
1 -
0.014 0.0175 0.0195
3 0.016 0.021 0.023
V
THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 34A, RL = 0.441, VGS = 4.5V, RGS = 6.8 (Figures 15, 21, 22) 14 90 28 32 160 90 ns ns ns ns ns ns RJC RJA (Figure 3) TO-220 and TO-263 1.20 62
oC/W oC/W
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S
Electrical Specifications
PARAMETER SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 1350 700 160 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID 35A, RL = 0.429 Ig(REF) = 1.0mA (Figures 14, 19, 20) 4.50 10.30 nC nC 37 19 1.4 45 23 1.7 nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 56A, RL = 0.268, VGS = 10V, RGS = 8.2 (Figures 16, 21, 22) 11 30 68 35 62 155 ns ns ns ns ns ns TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 35A ISD = 35A, dISD/dt = 100A/s ISD = 35A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 60 105 UNITS V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) 60 50 VGS = 10V 40 VGS = 4.5V 30 20 10 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S Typical Performance Curves
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 SINGLE PULSE 0.01 10-5 10-4 10 -2 10-3 10 -1 t, RECTANGULAR PULSE DURATION (s) NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 100 10 1
(Continued)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000 TC = 25oC FOR TEMPERATURES ABOVE 25 oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 10V I
1000 IDM, PEAK CURRENT (A)
=
I25
150 - TC 125
VGS = 5V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 -4 10-3 10-2 t , PULSE WIDTH (s) 10 -1 100 101
50 10-5
FIGURE 4. PEAK CURRENT CAPABILITY
1000
ID, DRAIN CURRENT (A)
100s 100
I AS, AVALANCHE CURRENT (A)
TJ = MAX RATED TC = 25o C
1000
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD ) +1]
100 STARTING TJ = 25oC STARTING TJ = 150oC
1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1
10
BVDSS MAX = 30V 100 1 0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 100
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S Typical Performance Curves
80 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) 60
(Continued)
-40oC 150 oC 25oC ID, DRAIN CURRENT (A)
80
VGS = 4.5V 60 VGS = 10V 40
VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 4V
40
VGS = 3.5V
20
20
VGS = 3V
VDD = 15V 0 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 0 0 1 2 3 4 5
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
30 ID = 56A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
25 ID = 35A 20 ID = 20A 15
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.6
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, I D = 56A
1.4
1.2
1.0
10 2 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 4 10
0.8 -60
-0 60 120 TJ, JUNCTION TEMPERATURE (oC)
180
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 1.1 NORMALIZED GATE THRESHOLD VOLTAGE 1.0 0.9 0.8 0.7 0.6 -60 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A
1.15 ID = 250A 1.10
1.05
1.00
0.95
0 60 120 TJ, JUNCTION TEMPERATURE (oC)
180
0.90 -60
0 60 160 TJ , JUNCTION TEMPERATURE (oC)
180
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S Typical Performance Curves
2000
(Continued)
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
1600
CISS
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + C GD
10 VDD = 15V 8
1200 COSS 800
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 56A ID = 35A ID = 20A 0 10 20 Qg, GATE CHARGE (nC) 30 40
400 CRSS 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
2
0
NOTE: Refer to Fairchild Application Notes 7254 and 7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
300
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
400 VGS = 4.5V, VDD = 15V, I D = 34A, R L = 0.441 tr SWITCHING TIME (ns) SWITCHING TIME (ns) 300
VGS = 10V, VDD = 15V, I D = 56A, R L = 0.268 250 td(OFF) 200 150 100 tr 50 td(ON) tf
200
tf td(OFF)
100
td(ON)
0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
0
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S Test Circuits and Waveforms
VDS RL VDD VDS VGS = 10 VGS
+
(Continued)
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S PSPICE Electrical Model
SUBCKT HUF76129 2 1 3 ;
CA 12 8 1.95e-9 CB 15 14 2.06e-9 CIN 6 8 1.18e-9
10
REV August 1998
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 33.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.02e-9 LSOURCE 3 7 3.45e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.3e-3 RGATE 9 20 3.5 RLDRAIN 2 5 10 RLGATE 1 9 40.2 RLSOURCE 3 7 34.5 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 8e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*1000),3.5))} .MODEL DBODYMOD D (IS = 1e-12 IKF = 10 RS = 5.6e-3 TRS1 = 5e-4 TRS2 = 1e-6 CJO = 2.23e-9 TT = 2e-7 M = 4e-1 N = 9.9e-1 XTI =4.75 ) .MODEL DBREAKMOD D (RS = 1.5e-1 IS = 1e-14 TRS1 = 9e-4 TRS2 = -2e-5 IKF = 1e-1) .MODEL DPLCAPMOD D (CJO = 1.12e-9 IS = 1e-30 N = 10 M = 6.7e-1 VJ = 1.45) .MODEL MMEDMOD NMOS (VTO = 2 KP = 5.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6) .MODEL MSTROMOD NMOS (VTO = 2.3 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.62 KP =2e-2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36) .MODEL RBREAKMOD RES (TC1 = 9.8e-4 TC2 = -1e-10) .MODEL RDRAINMOD RES (TC1 = 2e-2 TC2 = 1e-7) .MODEL RSLCMOD RES (TC1 = 1e-6 TC2 = 1.05e-6) .MODEL RSOURCEMOD RES (TC1 = 5e-4 TC2 = 1e-5) .MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1.1e-5) .MODEL RVTEMPMOD RES (TC1 = -1.65e-3 TC2 = 1.45e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.3 VOFF = -2.0) VON = -2.0 VOFF = -4.3) VON = -0.8 VOFF = 0.5) VON = 0.5 VOFF = -0.8)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2003 Fairchild Semiconductor Corporation
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S Saber Electrical Model
nom temp=25 deg c REV August 1998
template huf76129 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is=1.e-12, xti=4.75, cjo=2.23e-9,tt=20e-8, m=4e-1, n=9.9e-1) d..model dbreakmod = (is=1e-14) d..model dplcapmod = (cjo=1.12e-9,is=1e-30,n=10,m=6.7e-1, vj=1.45,) m..model mmedmod = (type=_n,vto=2,kp=5.75,is=1e-30, tox=1) DPLCAP m..model mstrongmod = (type=_n,vto=2.3,kp=80,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.62,kp=2e-2,is=1e-30, tox=1) 10 sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.3,voff=-2) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4.3) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.5) RSLC2 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-0.8) c.ca n12 n8 = 1.95e-9 c.cb n15 n14 = 2.06e-9 c.cin n6 n8 = 1.18e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.02e-9 l.lsource n3 n7 = 3.45e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9.8e-4,tc2=-1e-9 res.rdbody n71 n5 =5.6e-3, tc1=5e-4, tc2=1e-6 res.rdbreak n72 n5 =1.5e-1, tc1=9e-4, tc2=-2e-5 res.rdrain n50 n16 = 1.3e-3, tc1=2e-2,tc2=1e-7 res.rgate n9 n20 = 3.5 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 40.2 res.rlsource n3 n7 = 34.5 res.rslc1 n5 n51 = 1e-6, tc1=1e-6,tc2=-1.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 8e-3, tc1=5e-4,tc2=1e-5 res.rvtemp n18 n19 = 1, tc1=-1.65e-3,tc2=1.45e-9 res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-1.1e-5 spe.ebreak n11 n7 n17 n18 = 33.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/1000))** 3.5 )) } }
S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT
30v LL Ultrafet
LDRAIN 5 RLDRAIN RDBREAK 72 DBREAK 11 MWEAK DBODY MMED MSTRO EBREAK + 17 18 71 RDBODY DRAIN 2 RSLC1 51 ISCL 50
ESG + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
RDRAIN 21 16
8
RSOURCE
LSOURCE 7 RLSOURCE
SOURCE 3
15
RBREAK 17 18 RVTEMP 19
VBAT +
-
-
8 RVTHRES
22
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
HUF76129P3, HUF76129S3S SPICE Thermal Model
th JUNCTION
REV August 1998 HUF76129 CTHERM1 th 6 1.10e-5 CTHERM2 6 5 2.70e-2 CTHERM3 5 4 3.90e-2 CTHERM4 4 3 1.00e-2 CTHERM5 3 2 2.30e-2 CTHERM6 2 tl 1.80 RTHERM1 th 6 1.00e-4 RTHERM2 6 5 5.00e-4 RTHERM3 5 4 2.90e-2 RTHERM4 4 3 4.80e-1 RTHERM5 3 2 2.80e-1 RTHERM6 2 tl 1.00e-1
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
Saber Thermal Model
Saber thermal model HUF76129 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 =1.10e-5 ctherm.ctherm2 c2 c3 =2.70e-2 ctherm.ctherm3 c3 c4 =3.90e-2 ctherm.ctherm4 c4 c5 =1.00e-2 ctherm.ctherm5 c5 c6 =2.30e-2 ctherm.ctherm6 c6 tl=1.80 rtherm.rtherm1 th c2 =1.00e-4 rtherm.rtherm2 c2 c3 =5.00e-4 rtherm.rtherm3 c3 c4 =2.90e-2 rtherm.rtherm4 c4 c5 =4.80e-1 rtherm.rtherm5 c5 c6 =2.80e-1 rtherm.rtherm6 c6 tl=1.00e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1
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ImpliedDisconnectTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM
PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM
SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TruTranslationTM UHCTM UltraFET(R) VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I2

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